1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a semiconductor package and method for fabricating the same having a fan-out type chip size package (CSP) structure.
2. Background of the Related Art
In general, packaging technology for Integrated Circuits (ICs) has been developed to meet the needs for miniaturization and the reliability of packaging.
The need for miniaturization accelerates the development of a package close in size to a chip scale, and the need for the reliability of packaging encourages package fabricating technology which can improve efficiency of packaging and the mechanical and electrical reliability after packaging.
For a fan-in structure, solder balls are arrayed on the inner part of chip, which radiates heat. For a fan-out structure, solder balls are arrayed on the outer part of chip, to be projected, as well as the inner part of chip.
The related art semiconductor package will be described with reference to FIG. 1. As shown in FIG. 1, the related art semiconductor package includes a unit semiconductor chip 1 and two elastomers 2. The elastomers 2 are separated from each other on the upper part of the unit semiconductor chip 1 and extend to the exterior of both sides of the unit semiconductor chip 1.
A solder mask layer 3 is formed to be laid over the upper part of the separated elastomers 2, and a metal layer (not shown) is formed in one line direction along the surface of the elastomer 2 and the unit semiconductor chip 1. The solder mask layer 3 has a plurality of holes in the direction of a plurality of columns to expose the metal layer (not shown) on the upper part of the elastomer 2, and solder balls 4 are arranged in the holes to be in contact with the metal layer. In FIG. 1, three rows are on each side of the elastomers 2, each row consisting of four solder balls. The solder balls 4 in the outmost row are partially exposed to the outside of semiconductor chip 1 to form a fan-out structure.
In the above related art, an extra substrate such as the elastomer 2 is needed if the size of the semiconductor chip is reduced. Also, a capsule or supporter 5 is provided to enclose sides of the semiconductor chip 1, the elastomer 2 and the solder mask layer 3, thereby preventing the elastomer 2 from warping.
However, the related art semiconductor package has several problems. First, if the size of the chip 1 is changed, the extra substrate and the extra equipment for fabricating the same are needed to obtain the fan-out type chip scale package corresponding to the changed chip size. In addition, the thick capsule or supporter 5 is needed to prevent the substrate warpage. This complicates the package fabricating process.
Accordingly, the present invention is directed to a semiconductor package and fabricating method the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, a semiconductor package according to the present invention includes a unit semiconductor chip; a first stress buffer layer contacting the unit semiconductor chip on two sides of the unit semiconductor chip; at least one bonding pad arrayed on an upper part of the unit semiconductor chip; a second stress buffer layer formed over the first stress buffer layer and the unit semiconductor chip such that an upper surface of each bonding pad is exposed; at least one conducting line formed over the second stress buffer layer such that each conducting line contacts the upper surface of a respective bonding pad; a solder mask layer formed over the at least one conducting line and the second stress buffer layer, and having a plurality of holes therein to expose at least one region of each conducting line; and a plurality of solder balls formed in the holes to contact each conducting line.
In another aspect, a fabricating method of a semiconductor package includes forming bonding pads to be arrayed on different portions of a wafer defined by scribe lanes; attaching a first adhesive tape on the back of the wafer; dividing the wafer into a plurality of unit semiconductor chips, each chip containing at least one bonding pad, by cutting the scribe lanes; increasing a distance between the unit semiconductor chips by extending the first adhesive tape; forming a first stress buffer layer over the unit semiconductor chips; forming a second stress buffer layer over the first stress buffer layer and the unit semiconductor chips so as to expose an upper surface of each bonding pad; forming conducting lines over the second stress buffer respectively contacting the exposed upper surface of each bonding pad; forming a solder mask layer having a plurality of holes to expose at least one region of each conducting line; adhering solder balls in the holes to contact corresponding conducting lines; and forming unit semiconductor chip size packages by sequentially cutting the solder mask layer, the conducting lines, the second stress buffer layer, and the first stress buffer layer.
An advantage of the present invention is the provision of a semiconductor package and fabricating method for the same, in which solder balls are easily arranged in a fan-out type structure and the package fabricating process is simply performed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.